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? semiconductor components industries, llc, 2010 december, 2010 ? rev. 7 1 publication order number: cat5251/d cat5251 quad digitally program- mable potentiometer (dpp ) with 256 taps and spi interface description the cat5251 is four digitally programmable potentiometers (dpps ) integrated with control logic and 16 bytes of nvram memory. each dpp consists of a series of resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper outputs with cmos switches. a separate 8 ? bit control register (wcr) independently controls the wiper tap switches for each dpp. associated with each wiper control register are four 8 ? bit non ? volatile memory data registers (dr) used for storing up to four wiper settings. writing to the wiper control register or any of the non ? volatile data registers is via a spi serial bus. on power ? up, the contents of the first data register (dr0) for each of the four potentiometers is automatically loaded into its respective wiper control register. the cat5251 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. it is available in the ? 40 c to 85 c industrial operating temperature range and offered in a 24 ? lead soic and tssop package. features ? four linear ? taper digitally programmable potentiometers ? 254 resistor taps per potentiometer ? end to end resistance 50 k or 100 k ? potentiometer control and memory access via spi interface ? low wiper resistance, typically 100 ? nonvolatile memory storage for up to four wiper settings for each potentiometer ? automatic recall of saved wiper settings at power up ? 2.5 to 6.0 volt operation ? standby current less than 1 a ? 1,000,000 nonvolatile write cycles ? 100 year nonvolatile memory data retention ? soic 24 ? lead and tssop 24 ? lead ? industrial temperature range ? these devices are pb ? free, halogen free/bfr free and are rohs compliant http://onsemi.com tssop ? 24 y suffix case 948ar pin connections soic ? 24 (w) tssop ? 24 (y) (top view) hold so a0 r w3 1 r h3 r l3 sck r l2 r h2 r w2 soic ? 24 w suffix case 751bk see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information nc gnd r w1 r h1 r l1 nc v cc r l0 r h0 r w0 cat5251 a1 si cs wp
cat5251 http://onsemi.com 2 l = assembly location 3 = lead finish ? matte ? tin b = product revision (fixed as ?b?) cat = fixed as ?cat? 5251w = device code t = temperature range (i = industrial) ? = dash rr = resistance 25 = 2.5 k 10 = 10 k 50 = 50 k 00 = 100 k y = production year (last digit) m = production month (1-9, o, n, d) xxxx = last four digits of assembly lot number l3b cat5251wt ? rrymxxxx r = resistance 1 = 2.5 k 2 = 10 k 4 = 50 k 5 = 100 k l = assembly location b = product revision (fixed as ?b?) cat5251y = device code t = temperature range (i = industrial) 3 = lead finish ? matte ? tin y = production year (last digit) m = production month (1 ? 9, o, n, d) xxx = last three digits of assembly lot number rlb cat5251yt 3ymxxx marking diagrams (tssop ? 24) (soic ? 24)
cat5251 http://onsemi.com 3 figure 1. functional diagram a0 a1 nonvolatile data registers wiper control registers control logic spi bus interface sck si so r w0 r w1 r w2 r w3 r l3 r l2 r l1 r l0 r h3 r h2 r h1 r h0 wp hold cs pin descriptions si: serial input si is the serial data input pin. this pin is used to input all opcodes, byte addresses and data to be written to the cat5251. input data is latched on the rising edge of the serial clock. so: serial output so is the serial data output pin. this pin is used to transfer data out of the cat5251. during a read cycle, data is shifted out on the falling edge of the serial clock. sck: serial clock sck is the serial clock pin. this pin is used to synchronize the communication between the microcontroller and the cat5251. opcodes, byte addresses or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck. a0, a1: device address inputs these inputs set the device address when addressing multiple devices. a total of four devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5251. r h , r l : resistor end points the four sets of r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the four r w pins are equivalent to the wiper terminal of a mechanical potentiometer. cs : chip select cs is the chip select pin. cs low enables the cat5251 and cs high disables the cat5251. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway). the cat5251 draws zero current in the standby mode. a high to low transition on cs is required prior to any sequence being initiated. a low to high transition on cs after a valid write sequence is what initiates an internal write cycle. wp : write protect wp is the write protect pin. the write protect pin will allow normal read/write operations when held high. when wp is tied low, all non ? volatile write operations to the data registers are inhibited (change of wiper control register is allowed). wp going low while cs is still low will interrupt a write to the registers. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation. hold : hold the hold pin is used to pause transmission to the cat5251 while in the middle of a serial sequence without having to re ? transmit entire sequence at a later time. to pause, hold must be brought low while sck is low. the so pin is in a high impedance state during the time the part is paused, and transitions on the si pins will be ignored. to resume communication, hold is brought high, while sck is low. (hold should be held high any time this function is not being used.) hold may be tied high directly to v cc or tied to v cc through a resistor.
cat5251 http://onsemi.com 4 table 1. pin description pin # name function 1 so serial data output 2 a0 device address, lsb 3 r w3 wiper terminal for potentiometer 3 4 r h3 high reference terminal for potentiometer 3 5 r l3 low reference terminal for potentiometer 3 6 nc no connect 7 v cc supply voltage 8 r l0 low reference terminal for potentiometer 0 9 r h0 high reference terminal for potentiometer 0 10 r w0 wiper terminal for potentiometer 0 11 cs chip select 12 wp write protection 13 si serial input 14 a1 device address 15 r l1 low reference terminal for potentiometer 1 16 r h1 high reference terminal for potentiometer 1 17 r w1 wiper terminal for potentiometer 1 18 gnd ground 19 nc no connect 20 r w2 wiper terminal for potentiometer 2 21 r h2 high reference terminal for potentiometer 2 22 r l2 low reference terminal for potentiometer 2 23 sck bus serial clock 24 hold hold serial bus protocol the cat5251 supports the spi bus data transmission protocol. the synchronous serial peripheral interface (spi) helps the cat5251 to interface directly with many of today?s popular microcontrollers. the cat5251 contains an 8 ? bit instruction register. the instruction set and the operation codes are detailed in table 13, instruction set on page 9. after the device is selected with cs going low the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op ? codes that define the operation to be performed. device operation the cat5251 is four resistor arrays integrated with an spi serial interface logic, four 8 ? bit wiper control registers and sixteen 8 ? bit, non ? volatile memory data registers. each resistor array contains 255 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non ? volatile memory data registers via the spi bus. additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer?s non ? volatile data registers. also, the device can be instructed to operate in an ?increment/ decrement? mode. table 2. absolute maximum ratings parameter ratings units temperature under bias ? 55 to +125 c storage temperature ? 65 to +150 c voltage on any pin with respect to v ss (notes 1, 2) ? 2.0 to +v cc +2.0 v v cc with respect to ground ? 2.0 to +7.0 v package power dissipation capability (t a = 25 c) 1.0 w lead soldering temperature (10 s) 300 c wiper current 6 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the minimum dc input voltage is ?0.5 v. during transitions, inputs may undershoot to ?2.0 v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods of less than 20 ns. 2. latch ? up protection is provided for stresses up to 100 ma on address and data pins from ?1 v to v cc + 1 v.
cat5251 http://onsemi.com 5 table 3. recommended operating conditions parameter ratings units v cc +2.5 v to +6 v operating ambient temperature (industrial) ? 40 to +85 c table 4. potentiometer characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min typ max units r pot potentiometer resistance ( ? 00) 100 k r pot potentiometer resistance ( ? 50) 50 k potentiometer resistance tolerance 20 % r pot matching 1 % power rating 25 c, each pot 50 mw i w wiper current 3 ma r w wiper resistance i w = 3 ma @ v cc = 3 v 200 300 i w = 3 ma @ v cc = 5 v 100 150 v term voltage on any r h or r l pin v ss = 0 v gnd v cc v v n noise (note 3) nv/ hz resolution 0.4 % absolute linearity (note 4) r w(n)(actual) ? r (n)(expected) (note 7) 1 lsb (note 6) relative linearity (note 5) r w(n+1) ? [r w(n)+lsb ] (note 7) 0.5 lsb (note 6) tc rpot temperature coefficient of r pot (note 3) 300 ppm/ c tc ratio ratiometric temp. coefficient (note 3) 20 ppm/ c c h /c l /c w potentiometer capacitances (note 3) 10/10/25 pf fc frequency response r pot = 50 k (note 3) 0.4 mhz 3. this parameter is tested initially and after a design or process change that affects the parameter. 4. absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 6. lsb = r tot / 255 or (r h ? r l ) / 255, single pot 7. n = 0, 1, 2, ..., 255. table 5. d.c. operating characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min typ max units i cc1 power supply current f sck = 2.5 mhz, so open v cc = 6 v inputs = gnd 1 ma i cc2 power supply current non ? volatile write f sck = 2.5 mhz, so = open v cc = 6 v inputs = gnd 5 ma i sb standby current (v cc = 5.0 v) v in = gnd or v cc ; so open 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage ? 1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3 v) i ol = 3 ma 0.4 v v oh1 output high voltage (v cc = 6 v) i oh = ? 1.6 ma v cc ? 0.8 v
cat5251 http://onsemi.com 6 table 6. pin capacitance (note 8) (applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0 v (unless otherwise noted).) symbol parameter test conditions min typ max units c out output capacitance (so) v out = 0 v 8 pf c in input capacitance (cs , sck, si, wp , hold , a0, a1 v in = 0 v 6 pf table 7. a.c. characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min typ max units t su data setup time c l = 50 pf 50 ns t h data hold time 50 ns t wh sck high time 125 ns t wl sck low time 125 ns f sck clock frequency dc 3 mhz t lz hold to output low z 50 ns t ri (note 8) input rise time 2 s t fi (note 8) input fall time 2 s t hd hold setup time 100 ns t cd hold hold time 100 ns t v output valid from clock low 200 ns t ho output hold time 0 ns t dis output disable time 250 ns t hz hold to output high z 100 ns t cs cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns table 8. power up timing (notes 8, 9) (over recommended operating conditions unless otherwise stated.) symbol parameter min typ max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 8. this parameter is tested initially and after a design or process change that affects the parameter. 9. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. table 9. wiper timing symbol parameter min max units t wrpo wiper response time after power supply stable 5 10 s t wrl wiper response time after instruction issued 5 10 s table 10. write cycle limits (over recommended operating conditions unless otherwise stated.) symbol parameter min typ max units t wr write cycle time 5 ms
cat5251 http://onsemi.com 7 table 11. reliability characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter reference test method min typ max units n end (note 10) endurance mil ? std ? 883, test method 1033 1,000,000 cycles/byte t dr (note 10) data retention mil ? std ? 883, test method 1008 100 years v zap (note 10) esd susceptibility mil ? std ? 883, test method 3015 2000 v i lth (note 10) latch ? up jedec standard 17 100 ma 10. this parameter is tested initially and after a design or process change that affects the parameter. figure 2. sychronous data timing valid in hi ? z hi ? z sck si so note: dashed line = mode (1, 1) t css t su t h t cs t csh t dis t ho t ri t fi t wl t v t wh v ih v il cs v ih v il v ih v il v oh v ol figure 3. hold timing sck so high impedance hold cs t hd t cd t hz t hd t cd t lz
cat5251 http://onsemi.com 8 instruction and register description device type / address byte the first byte sent to the cat5251 from the master/processor is called the device address byte. the most significant four bits of the device type address are a device type identifier. these bits for the cat5251 are fixed at 0101[b] (refer to figure 4). the two least significant bits in the slave address byte, a1 ? a0, are the internal slave address and must match the physical device address which is defined by the state of the a1 ? a0 input pins for the ca t5251 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a1 ? a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the device address byte must be set to 0. instruction byte the next byte sent to the cat5251 contains the instruction and register pointer information. the four most significant bits used provide the instruction opcode i3 ? i0. the r1 and r0 bits point to one of the four data registers of each associated potentiometer. the least two significant bits point to one of four wiper control registers. the format is shown in figure 5. table 12. data register selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 figure 4. identification byte format id3 id2 id1 id0 0 0 a1 a0 0101 (msb) (lsb) device type identifier slave address figure 5. instruction byte format i3 i2 i1 i0 r1 r0 p1 p0 (msb) (lsb) instruction data register wcr/pot selection opcode selection
cat5251 http://onsemi.com 9 wiper control and data registers wiper control register (wcr) the cat5251 contains four 8 ? bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via w rite wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction; it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power ? up. the wiper control register is a volatile register that loses its contents when the ca t5251 is powered ? down. although the register is automatically loaded with the value in dr0 upon power ? up, this may be dif ferent from the value present at power ? down. data registers (dr) each potentiometer has four 8 ? bit non ? volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non ? volatile operation and will take a maximum of 5 ms. if the application does not require storage of multiple settings for the potentiometer; the data registers can be used as standard memory locations for system parameters or user preference data. write in process the contents of the data registers are saved to nonvolatile memory when the cs input goes high after a write sequence is received. the status of the internal write cycle can be monitored by issuing a read status command to read the write in process (wip) bit. instructions four of the ten instructions are three bytes in length. these instructions are: ? read wiper control register ? read the current wiper position of the selected potentiometer in the wcr ? write wiper control register ? change current wiper position in the wcr of the selected potentiometer ? read data register ? read the contents of the selected data register ? write data register ? write a new value to the selected data register ? read status ? read the status of the wip bit which when set to ?1? signifies a write cycle is in progress. table 13. instruction set ( note: 1/0 = data is one or zero) instruction instruction set operations i3 i2 i1 i0 r1 r0 wcr1/p1 wcr0/p0 read wiper control register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper control register pointed to by p1 ? p0 write wiper control register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper control register pointed to by p1 ? p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1 ? p0 and r1 ? r0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1 ? p0 and r1 ? r0 xfr data register to wiper control register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1 ? p0 and r1 ? r0 to its associated wiper control register xfr wiper control register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper control register pointed to by p1 ? p0 to the data register pointed to by r1 ? r0 global xfr data registers to wiper control registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r1 ? r0 of all four pots to their respective wiper control registers global xfr wiper control registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1 ? r0 of all four pots increment/decrement wiper control register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p1 ? p0 read status (wip bit) 0 1 0 1 0 0 0 1 read wip bit to check internal write cycle status
cat5251 http://onsemi.com 10 the basic sequence of the three byte instructions is illustrated in figure 7. these three ? byte instructions exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non ? volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two ? byte sequence to complete, as illustrated in figure 6. these instructions transfer data between the host/processor and the cat5251; either between the host and one of the data registers or directly between the host and the wiper control register. these instructions are: ? xfr data register to wiper control register this transfers the contents of one specified data register to the associated wiper control register. ? xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. ? global xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. ? global xfr wiper counter register to data register this transfers the contents of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figures 8 and 9). the increment/decrement command is different from the other commands. once the command is issued the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 6. two ? byte instruction sequence 0101 a2 a0 i2 i1 i0 r1 r0 p1 si id3 id2 id1 id0 p0 device id internal instruction opcode address register address pot/wcr address a1 a3 i3 00 figure 7. three ? byte instruction sequence i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address wcr[7:0] or data register d[7:0] 0 10100 a2 a1 a0 p1 p0 si d7 d6 d5 d4 d3 d2 d1 d0 a3 figure 8. increment/decrement instruction sequence i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address 010100 a2 a1 a0 r0 p1 p0 si i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3
cat5251 http://onsemi.com 11 figure 9. increment/decrement timing limits sck si inc/dec command issued voltage out t wrl r w instruction format table 14. read wiper control register (wcr) cs device addresses instruction data cs 0 1 0 1 0 0 a1 a0 1 0 0 1 0 0 p1 p0 7 6 5 4 3 2 1 0 table 15. write wiper control register (wcr) cs device addresses instruction data cs 0 1 0 1 0 0 a1 a0 1 0 1 0 0 0 p1 p0 7 6 5 4 3 2 1 0 table 16. read data register (dr) cs device addresses instruction data cs 0 1 0 1 0 0 a1 a0 1 0 1 1 r1 r0 p1 p0 7 6 5 4 3 2 1 0 table 17. write data register (dr) cs device addresses instruction data cs high voltage write cycle 0 1 0 1 0 0 a1 a0 1 1 0 0 r1 r0 p1 p0 7 6 5 4 3 2 1 0 table 18. read status (wip) cs device addresses instruction data cs 0 1 0 1 0 0 a1 a0 0 1 0 1 0 0 0 1 7 6 5 4 3 2 1 w 0 0 0 0 0 0 0 i p
cat5251 http://onsemi.com 12 instruction format (continued) table 19. global transfer data register (dr) to wiper control register (wcr) cs device addresses instruction cs 0 1 0 1 0 0 a1 a0 0 0 0 1 r1 r0 0 0 table 20. global transfer wiper control register (wcr) to data register (dr) cs device addresses instruction cs high voltage write cycle 0 1 0 1 0 0 a1 a0 1 0 0 0 r1 r0 0 0 table 21. transfer wiper control register (wcr) to data register (dr) cs device addresses instruction cs high voltage write cycle 0 1 0 1 0 0 a1 a0 1 1 1 0 r1 r0 p1 p0 table 22. transfer data register (dr) to wiper control register (wcr) cs device addresses instruction cs 0 1 0 1 0 0 a1 a0 1 1 0 1 r1 r0 p1 p0 table 23. increment (i)/decrement (d) wiper control register (wcr) cs device addresses instruction data cs 0 1 0 1 0 0 a1 a0 0 0 1 0 0 0 p1 p0 i/d i/d . . . i/d i/d note: any write or transfer to the non ? volatile data registers is followed by a high voltage cycle after a stop has been issued.
cat5251 http://onsemi.com 13 package dimensions soic ? 24, 300 mils case 751bk ? 01 issue o e1 e a1 a2 e pin#1 identification b d c a top view side view end view 1 1 h h l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-013. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.31 0.20 0.25 15.20 10.11 7.34 1.27 bsc 2.65 0.30 0.51 0.33 0.75 15.40 10.51 7.60 l 0.40 1.27 2.35 a2 2.05 2.55 1 5o 15o
cat5251 http://onsemi.com 14 package dimensions tssop24, 4.4x7.8 case 948ar ? 01 issue a 1 a1 a2 d top view side view end view e e1 e b l c l1 a symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 7.70 6.25 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.70 7.90 6.55 4.50 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. 0.60 7.80 6.40 4.40
cat5251 http://onsemi.com 15 example of ordering information (note 13) prefix device # suffix company id cat 5251 w product number 5251 i ? t1 package i = industrial ( ? 40 c to +85 c) temperature range w: soic y: tssop t: tape & reel 1: 1,000 units / reel (soic) 2: 2,000 units / reel (tssop) tape & reel (note 14) (optional) ? 50 resistance ? 50: 50 k ? 00: 100 k table 24. ordering information orderable part number resistance (k ) package lead finish cat5251wi ? 50 ? t1 50 soic matte ? tin cat5251wi ? 00 ? t1 100 cat5251yi ? 50 ? t2 50 tssop cat5251yi ? 00 ? t2 100 cat5251wi50 50 soic cat5251wi00 100 cat5251yi50 50 tssop cat5251yi00 100 11. all packages are rohs ? compliant (lead ? free, halogen ? free). 12. the standard lead finish is matte ? tin. 13. the device used in the above example is a cat5251wi ? 50 ? t1 (soic, industrial temperature, 50 k , tape & reel, 1,000/reel). 14. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat5251/d dpp is a trademark of semiconductor components industries, llc. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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